Fast short-circuit protection for SiC MOSFETs in extreme short-circuit conditions by integrated functions in CMOS-ASIC technology

Wide bandgap power transistors such as SiC MOSFETs and HEMTs GaN push furthermore the classical compromises in power electronics. Briefly, significant gains have been demonstrated: better efficiency, coupled with an increase in power densities offered by the increase in switching frequency. HV SiC MOSFETs have specific features such as a low short-circuit SC withstand time capability compared to Si IGBTs and thinner gate oxide, and a high gate-to-source switching control voltage. The negative bias on the gate at the off-state creates additional stress which reduces the reliability of the SiC MOSFET. The high positive bias on the gate causes a large drain saturation current in the event of a SC. Thus, this technology gives rise to specific needs for ultrafast monitoring and protection. For this reason, the work of this thesis focuses on two studies to overcome these constraints, with the objective of reaching a good performance compromise between “CMS/ASIC-CMOS technological integration level-speed–robustness”. The first one, gathers a set of new solutions allowing a detection of the SC on the switching cycle, based on a conventional switch control architecture with two voltage levels. The second study is more exploratory and is based on a new gate-driver architecture, called multi-level, with low stress level for the SiC MOSFET while maintaining dynamic performances. The manuscript covers firstly the SiC MOSFET environment, (characterization and properties of SC behavior by simulation using PLECS and LTSpice software) and covers secondly a bibliographical study on the Gate drivers. And last, an in-depth study was carried out on SC type I & II (hard switch fault) (Fault under Load) and their respective detection circuits. A test bench, previously carried out in the laboratory, was used to complete and validate the analysis-simulation study and to prepare test stimuli for the design stage of new solutions. Inspired by the Gate charge method that appeared for Si IGBTs and evoked for SiC MOSFETs, this method has therefore been the subject of design, dimensioning and prototyping work, as a reference. This reference allows an HSF type detection in less than 200ns under 400V with 1.2kV components ranging from 80 to 120mOhm. Regarding new rapid and integrated detection methods, the work of this thesis focuses particularly on the design of a CMOS ASIC circuit. For this, the design of an adapted gate driver is essential. An ASIC is designed in X-Fab XT-0.18 SOICMOS technology under Cadence, and then packaged and assembled on a PCB. The PCB is designed for test needs and adaptable to the main bench. The design of the gate driver considered many functions (SC detection, SSD, segmented buffer, an "AMC", ...). From the SC detection point of view, the new integrated monitoring functions concern the VGS time derivative method which is based on a detection by an RC analog shunt circuit on the plateau sequence with two approaches: the first approach is based on a dip detection, i.e. the presence or not of the Miller plateau. The second approach is based on slope detection, i.e. the variability of the input capacitance of the power transistor under SC-HSF compared to normal operation. These methods are compared in the third chapter of the thesis, and demonstrate fault detection times between 40ns and 80ns, and preliminary robustness studies and critical cases are presented. A second new method is partially integrated in the ASIC, was designed. This method is not developed in the manuscript for valorization purposes. In addition to the main study, an exploratory study has focused on a modular architecture for close control at several bias voltage levels taking advantage of SOI isolation and low voltage CMOS transistors to drive SiC MOSFETs and improve their reliability through active and dynamic multi-level selection of switching sequences and on/off states

Protection rapide en régime extrême de court-circuit des transistors MOSFET SiC par fonctions intégrées en technologie ASIC CMOS

Les transistors de puissance grands gaps tels que les MOSFETs SiC et HEMT GaN repoussent les compromis classiques en électronique de puissance. Brièvement, des gains significatifs ont été démontrés par les transistors SiC et GaN: meilleurs rendements, couplés à une augmentation des densités de puissance offertes par la montée en fréquence de découpage. Les MOSFET SiC à haute tension présentent des spécificités telles qu'une faible tenue en court-circuit (SC) par rapport aux IGBT Si et un oxyde de grille aminci, et une tension de commande rapprochée grillesource élevée. La polarisation négative sur la grille à l'état bloqué crée un stress supplémentaire qui réduit la fiabilité du MOSFET SiC. La forte polarisation positive de la grille provoque un courant de saturation de drain important en cas de SC. Ainsi, cette technologie fait émerger des besoins spécifiques de surveillance et de protection ultra-rapides. Pour cela, le travail de cette thèse se focalise sur deux études pour surmonter ces contraintes toute en gardant un bon compromis de performances entre « niveau d’intégration technologique ‘CMS/ASIC-CMOS’–rapidité–robustesse ». La première, regroupe un ensemble de solutions nouvelles permettant une détection du courtcircuit sur le cycle de commutation, sur la base d'une architecture conventionnelle de commande rapprochée dite à 2 niveaux de tension. La deuxième étude est plus exploratoire et basée sur une nouvelle architecture de gate–driver, dite multi-niveaux, à faible niveau de stress pour le MOSFET SiC tout en maintenant les performances dynamiques. Les travaux portent tout d’abord sur l’environnement du SiC MOSFET, (caractérisation et propriétés de comportement en SC par simulations orientées "circuit" de type PLECS™ et LTSpice™), puis présentent une étude bibliographique sur les commandes rapprochées dites Gate Driver, une étude approfondie a été réalisée sur les court-circuits type I & II (Hard switch fault) (Fault under Load) ; regroupés dans un premier chapitre du manuscrit. Un banc de test réalisé antérieurement au sein du laboratoire, a permis de compléter et de valider l’étude d'analyse-simulation et de préparer des stimuli test pour l'étape de conception des nouvelles solutions. Inspirée par la méthode de Gate charge apparue pour les IGBTs en silicium et évoquée pour les MOSFETs SiC, cette première approche fait l'objet d'un travail de conception, de dimensionnement et de prototypage. Cette méthode de référence permet une détection de type HSF en moins de 200ns sous 0-600V avec des composants 1,2kV allant de 80 mOhm à 120mOhm. S'agissant des nouvelles méthodes de détection rapides et intégrées, les travaux de cette thèse se focalisent particulièrement sur la conception d’un circuit ASIC CMOS. Pour cela, la conception d’un gate driver adapté est essentiel. Un ASIC est conçu en technologie X-Fab XT-0,18μm SOICMOS sous Cadence™, et puis mis en boitier et assemblé sur PCB conçu pour les besoins de tests et adaptable au banc principal. La conception du gate driver a considéré de nombreuses fonctions (détection du SC, SSD Soft shut down, buffer segmenté, AMC Active Miller Clamp", …). Du point de vue de la détection du SC, les fonctions nouvelles de surveillance intégrées concernent la méthode de dérivation temporelle de VGS qui est basée sur une détection par un circuit dérivateur analogique RC sur la séquence de plateau avec deux variantes. Une deuxième méthode nouvelle partiellement intégrée dans l'ASIC a été conçu, non développé dans ce mémoire dans le but d’une valorisation. En marge de cette étude principale, une étude exploratoire a porté sur une nouvelle architecture modulaire de commande rapprochée à plusieurs niveaux de tension de polarisation tirant profit de l'isolation SOI et des transistors CMOS à basse tension pour piloter le MOSFETs SiC et améliorer leur fiabilité grâce à une sélection active et dynamique à plusieurs niveaux sur les séquences de commutation et les états marche/arrêt.Wide bandgap power transistors such as SiC MOSFETs and HEMTs GaN push furthermore the classical compromises in power electronics. Briefly, significant gains have been demonstrated: better efficiency, coupled with an increase in power densities offered by the increase in switching frequency. HV SiC MOSFETs have specific features such as a low short-circuit SC withstand time capability compared to Si IGBTs and thinner gate oxide, and a high gate-to-source switching control voltage. The negative bias on the gate at the off-state creates additional stress which reduces the reliability of the SiC MOSFET. The high positive bias on the gate causes a large drain saturation current in the event of a SC. Thus, this technology gives rise to specific needs for ultrafast monitoring and protection. For this reason, the work of this thesis focuses on two studies to overcome these constraints, with the objective of reaching a good performance compromise between “CMS/ASIC-CMOS technological integration level-speed–robustness”. The first one, gathers a set of new solutions allowing a detection of the SC on the switching cycle, based on a conventional switch control architecture with two voltage levels. The second study is more exploratory and is based on a new gate-driver architecture, called multi-level, with low stress level for the SiC MOSFET while maintaining dynamic performances. The manuscript covers firstly the SiC MOSFET environment, (characterization and properties of SC behavior by simulation using PLECS and LTSpice software) and covers secondly a bibliographical study on the Gate drivers. And last, an in-depth study was carried out on SC type I & II (hard switch fault) (Fault under Load) and their respective detection circuits. A test bench, previously carried out in the laboratory, was used to complete and validate the analysis-simulation study and to prepare test stimuli for the design stage of new solutions. Inspired by the Gate charge method that appeared for Si IGBTs and evoked for SiC MOSFETs, this method has therefore been the subject of design, dimensioning and prototyping work, as a reference. This reference allows an HSF type detection in less than 200ns under 400V with 1.2kV components ranging from 80 to 120mOhm. Regarding new rapid and integrated detection methods, the work of this thesis focuses particularly on the design of a CMOS ASIC circuit. For this, the design of an adapted gate driver is essential. An ASIC is designed in X-Fab XT-0.18 SOICMOS technology under Cadence, and then packaged and assembled on a PCB. The PCB is designed for test needs and adaptable to the main bench. The design of the gate driver considered many functions (SC detection, SSD, segmented buffer, an "AMC", ...). From the SC detection point of view, the new integrated monitoring functions concern the VGS time derivative method which is based on a detection by an RC analog shunt circuit on the plateau sequence with two approaches: the first approach is based on a dip detection, i.e. the presence or not of the Miller plateau. The second approach is based on slope detection, i.e. the variability of the input capacitance of the power transistor under SC-HSF compared to normal operation. These methods are compared in the third chapter of the thesis, and demonstrate fault detection times between 40ns and 80ns, and preliminary robustness studies and critical cases are presented. A second new method is partially integrated in the ASIC, was designed. This method is not developed in the manuscript for valorization purposes. In addition to the main study, an exploratory study has focused on a modular architecture for close control at several bias voltage levels taking advantage of SOI isolation and low voltage CMOS transistors to drive SiC MOSFETs and improve their reliability through active and dynamic multi-level selection of switching sequences and on/off states

Predictive gate ageing-laws of SiC MOSFET under repetitive short-circuit stress

International audienceThis paper proposes SiC MOSFET gate ageing-laws under repetitive short-circuit stress. Based on analytical studies, physical forms and preconditioning data, numerical fitting based on stress variables T j, T Pulse Gate Damage % and E sc is proposed. Accuracy and prediction capabilities of ageing-laws have been evaluated and compared. Resulting in suggesting a new ageing-law based on T Al_Top metal-source. This one gives the best fitting accuracy. Finally, the ageing-law based directly on the short-circuit energy E sc appears to have the best in prediction capability

Predictive gate ageing-laws of SiC MOSFET under repetitive short-circuit stress

International audienceThis paper proposes SiC MOSFET gate ageing-laws under repetitive short-circuit stress. Based on analytical studies, physical forms and preconditioning data, numerical fitting based on stress variables Tj, TPulse Gate Damage % and Esc is proposed. Accuracy and prediction capabilities of ageing-laws have been evaluated and compared. Resulting in suggesting a new ageing-law based on TAl_Top metal-source. This one gives the best fitting accuracy. Finally, the ageing-law based directly on the short-circuit energy Esc appears to have the best in prediction capability

Comparison between ig Integration and vgs Derivation methods dedicated to fast Short-Circuit 2D-Diagnosis for Wide Band Gap Power Devices

International audienceThis paper presents and compares two original high speed protection circuits, ig integration and vgs derivation methods against Short Circuit (SC) types, Hard Switch Fault (HSF) and Fault Under Load (FUL). Since the gate-drain capacitor Cgd of a power device depends on vds, it can become an original native sensor to monitor the switching operation and so detect unwanted vds transition or absence of vds transition by monitoring only vgs. Using only low-voltage monitoring is an essential step to integrate fast and embedded new detection methods on an ASIC gate driver. This Cgd capacitor plays a major part in the two detection methods. The first method is based on dedicated two-dimension monitoring of the gate charge transferred in a time interval combined with gate voltage monitoring. The second method consists of the reconstruction of the dvgs/dt by means of a capacitive current sensing to provide the vgs derivation combined with the vgs monitoring. Comparison and simulation of the methods based on a C2M0025120D SiC MOSFET device under LTspice™ are made to verify the validity of the methods. In terms of detection speed of the SC, a detection time of 300ns is obtained for both methods. Both methods are easy to design, and to integrate. However, the robustness and the speed of detection trade-off of all these methods will be analyzed and compared relatively to the critical functionalities

Comparison between i g integration and v gs derivation methods dedicated to fast short-circuit 2D diagnosis for wide bandgap power transistors

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CMOS Gate Driver with fast short circuit protection for SiC MOSFETs

International audienceThis article presents an alternative solution to the short circuit challenges commonly faced by SiC MOSFETs power transistors. In response to this issue, a dedicated fast CMOS active gate driver AGD is designed to detect the short circuits and to protect SiC MOSFETs, using only low voltage analog functions (5V and 40V transistors). The external high voltage diode used in the desaturation monitoring technique is no longer required and the short circuit detection can be much faster based only on signals observed by the gate driver. The IC prototype is based on XFAB XT018 0.18um CMOS SOI technology. The novel detection circuit is based on a 2D diagnosis, without any time dependency, fully integrated, with a low monitoring voltage. Detection of SC events is between 35ns and 130ns depending on the input capacitance of the power transistor, the internal/external resistors, detection threshold levels and other parameters

Modular Multilevel SOI-CMOS Active Gate Driver Architecture for SiC MOSFETs

International audienceHigh Voltage SiC power MOSFETs have specific driving challenges such as a reduced short circuit capability (compared to Si IGBTs) and a weak field oxide layer, a large gate to source driving voltage (compared to GaN FETs), a high electric field under negative gate bias in off-state and a high switching speed. The negative bias in off-state creates a high stress which reduces the reliability of the SiC MOSFET. The high positive gate bias can generate large drain saturation current in case of short circuit events. We propose a modular multilevel architecture, which takes benefits of SOI isolation and low voltage CMOS transistors to drive SiC MOSFETs and to improve their reliability using an active and dynamic multilevel-selection on the switching sequences and on/off states

Robustness study of a fast protection method based on the gate-charge dedicated for SiC MOSFETs power device

International audienceThis paper focuses on the extensive robustness validation of a gate charge detection method designed for SiC MOSFETs under short-circuit operation, and, in terms of failure-modes. The benefits of having a fast (submicrosecond-150ns) detection method is illustrated by a 1D thermo-metallurgical simulation. This method is integrated owing to an optimized SMD/PCB technology (Surface-Mount Device/ Printed Circuit Board)

VDS and VGS Depolarization Effect on SiC MOSFET Short-Circuit Withstand Capability Considering Partial Safe Failure-Mode

This paper presents a detailed analysis of 1200 V Silicon Carbide (SiC) power MOSFET exhibiting different short-circuit failure mechanisms and improvement in reliability by VDS and VGS depolarization. The device robustness has undergone an incremental pulse under different density decreasing; either drain-source voltage or gate-driver voltage. Unlike silicon device, the SiC MOSFET failure mechanism firstly displays specific gradual gate-cracks mechanism and progressive gate-damage accumulations greater than 4 µs/9 J·cm−2. Secondly, a classical drain-source thermal runaway appears, as for silicon devices, in a time greater than 9 µs. Correlations with short-circuit energy measurements and temperature simulations are investigated. It is shown that the first mechanism is an incremental soft gate-failure-mode which can be easily used to detect and protect the device by a direct feedback on the gate-driver. Furthermore, it is highlighted that this new mechanism can be sufficiently consolidated to avoid the second drain-source mechanism which is a hard-failure-mode. For this purpose, it is proposed to sufficiently depolarize the on-state gate-drive voltage to reduce the chip heating-rate and thus to decouple the failure modes. The device is much more robust with a short-circuit withstand time higher than 10 µs, as in silicon, no risk of thermal runaway and with an acceptable penalty on RDS-ON